1. Field of the Invention
This invention relates to computer processors, and more particularly to the realignment of a floating point pipeline to an integer pipeline.
2. Description of the Related Art
Pipelined microprocessors are well-known. These processors have a main pipeline or pipelines for executing standard integer operations. However, floating point operations are so complex that the integer pipelines are not able to efficiently process these floating point operations. A separate floating point unit (FPU) such as a co-processor has been used to efficiently process these floating point operations. More recently, the FPU has been integrated onto the microprocessor chip. Thus the FPU, which is itself pipelined, acts as an additional pipeline in the microprocessor.
Dual-Instruction-Set Processor for RISC and CISC
A new type of microprocessor has been invented that can process instructions from two different instruction sets. For example, a complex instruction set computer (CISC) instruction set may be processed on a reduced instruction set computer (RISC) microprocessor, as described in "Dual-Instruction-Set Architecture CPU with Hidden Software Emulation Mode", U.S. application Ser. No. 08/179,926, assigned to this application's assignee. In this dual-instruction-set processor, the second CISC instruction set is not merely emulated in software, but many of the simpler CISC instructions are directly executed in the RISC pipeline. The more complex CISC instructions are emulated by routines of RISC instructions.
This dual-instruction-set processor had a problem that was addressed in the parent application, "Pipeline with Temporal Re-Arrangement of Functional Units for Dual-Instruction Set CPU", U.S. application Ser. No. 08/361,017. The problem was that CISC instructions use memory operands while RISC instructions use only register operands. Thus for RISC operations, the pipeline is most efficient when the memory access stages of the pipeline are located late in the pipeline, such as in the execute stage. However, for CISC operations the memory access stages must be located early in the pipeline, before the execute stage so they can deliver a memory operand to the execute stage.
Efficient Dual-Pipeline Moves Execute Hardware to Different Stages
The solution to the problem of pipeline efficiency was to allow the execute hardware to "move" in the time and sequence of the pipestages to an earlier stage for RISC operations, but move to later stages for CISC operations. Thus the pipeline for CISC was arranged:
D A C M/X W PA1 D A/X C M W
but for RISC was re-arranged to:
where D is the decode stage, A the address generate stage, C the cache access stage, M the memory access stage, and W the write-back stage. X is the execution hardware such as the arithmetic-logic-unit (ALU). The execution hardware appears in the 4th (M) stage for CISC, allowing a memory operand to be fetched from the cache before the ALU. The pipeline is re-arranged for RISC to use the ALU in the 2nd (A) stage. Thus the RISC pipeline arrangement has reduced latency until the execute occurs, which improves performance.
Floating Point Instructions
Floating point instructions also differ with the RISC and CISC instruction sets. RISC floating point instructions use register operands, while CISC floating point instructions first fetch an operand from memory before the operation is performed. Thus the basic pipeline for RISC and CISC floating point instructions also differ in requirements. A simple execute or load-only pipeline works best with RISC, but CISC requires a more complex load-first-then-execute pipeline.
However, the floating point pipeline does not contain load/store hardware. Thus the integer pipelines must be used for load and store operations. While this is not a problem for RISC instructions, since the load operations do not also use the floating point pipeline, CISC instructions must use both the load/store integer pipeline and then the floating point pipeline. Coordination between the integer and floating point pipelines is critical.
What is desired is a processor having a floating point pipeline coordinated with integer pipelines. It is desired to execute both CISC and RISC floating point instructions in the floating point pipeline, but without adding memory fetch stages or hardware to the floating point pipeline.